The search algorithm is a key router technology. At the prophase, the Ternary Content Addressable Memory (TCAM) is adopted to store and forward table entries.
The range search algorithm is a mature common algorithm technology that adopts the ternary tree and binary tree data structures.
For table entries that adopt longest-match, each node of the ternary tree includes Key value information and mask length information. Through the Key value information and the mask length information, a table entry can be expressed as a range. For example, the table entry 1.1.1.1/24 indicates the range from 1.1.1.0 to 1.1.1.255. That is, all destination addresses within the range are matched to 1.1.1.1/24. In this way, a routing table entry with a mask is turned into a range indicated by two nodes Likewise, all routing table entries can be turned into a series of ranges, and the nodes within these ranges are stored in ordinary binary trees.
The conventional art adopts the Central Processing Unit (CPU) in the Field Programmable Gate Array (FPGA) to insert and delete the series of table entries. The preceding method, however, leads to a large number of read/write operations on the storage media. In certain cases, a large number of table entries need to be moved in order to search for idle space. In extreme cases, to insert a table entry, all existing table entries need to be moved. In random cases, when the capacity reaches a certain value, the search speed of the preceding method is slow. Thus, the preceding method cannot support a high refresh rate.
For table entries with different bit widths, the conventional art needs to implement strict restrictions on base addresses. For a table entry with 64 bits, the conventional art still adopts the 32-bit addressing. As the number of table entries increases, the base addresses multiply as follows:                Base addresses for table entries on Page0: 0, 1, 2, . . .        Base addresses for table entries on Page1: 2, 4, 6, . . .        Base addresses for table entries on Page2: 4, 8, 12, . . .        Base addresses for table entries on Page4: 8, 16, 24, . . .        
Therefore, as the table capacity increases, a large number of table entries are moved inevitably. The larger the table capacity is, the more frequently all table entries are moved. Such a restriction complicates the table entry resource management. When certain specific base addresses are occupied by other table entries, the conventional art has strict restrictions on the base addresses of table entries with different bit widths. As a result, the capacity is greatly wasted. In addition, as the number of table entries increases, the base addresses multiply. This results in a large number of movement operations and increases the algorithm maintenance cost.